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SN54LV240A, SN74LV240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS384F - SEPTEMBER 1997 - REVISED JULY 2003
D D D D D D D
2-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25C Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
SN54LV240A . . . J OR W PACKAGE SN74LV240A . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW)
1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
These octal buffers/drivers are designed for 2-V to 5.5-V VCC operation. The 'LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. ORDERING INFORMATION
TA PACKAGE SOIC - DW SOP - NS -40C 85C -40 C to 85 C SSOP - DB TSSOP - PW TVSOP - DGV CDIP - J -55C 125C -55 C to 125 C CFP - W LCCC - FK Tube of 25 Reel of 2000 Reel of 2000 Reel of 2000 Tube of 70 Reel of 2000 Reel of 250 Reel of 2000 Tube of 20 Tube of 85 Tube of 55 ORDERABLE PART NUMBER SN74LV240ADW SN74LV240ADWR SN74LV240ANSR SN74LV240ADBR SN74LV240APW SN74LV240APWR SN74LV240APWT SN74LV240ADGVR SNJ54LV240AJ SNJ54LV240AW SNJ54LV240AFK
1A2 2Y3 1A3 2Y2 1A4
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2Y4 1A1 1OE VCC
2OE 1Y1 2A4 1Y2 2A3 1Y3
description/ordering information
SN54LV240A . . . FK PACKAGE (TOP VIEW)
SNJ54LV240AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2Y1 GND 2A1 1Y4 2A2
TOP-SIDE MARKING LV240A 74LV240A LV240A LV240A LV240A SNJ54LV240AJ SNJ54LV240AW
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SN54LV240A, SN74LV240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS384F - SEPTEMBER 1997 - REVISED JULY 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y L H Z
logic diagram (positive logic)
1OE 1 2OE 19
1A1
2
18
1Y1
2A1
11
9
2Y1
1A2
4
16
1Y2
2A2
13
7
2Y2
1A3
6
14
1Y3
2A3
15
5
2Y3
1A4
8
12
1Y4
2A4
17
3
2Y4
2
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SN54LV240A, SN74LV240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS384F - SEPTEMBER 1997 - REVISED JULY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SN54LV240A, SN74LV240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS384F - SEPTEMBER 1997 - REVISED JULY 2003
recommended operating conditions (see Note 4)
SN54LV240A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 High or low state 3-state VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC 5.5 -50 -2 -8 -16 50 2 8 16 200 100 0 0 0 MAX 5.5 SN74LV240A MIN 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC 5.5 -50 -2 -8 -16 50 2 8 16 200 100 ns/V mA A mA V V MAX 5.5 UNIT V
VIH
High-level input voltage
VIL
Low-level input voltage
VI VO
Input voltage Output voltage
V V A
IOH
High-level output current
IOL
Low-level output current
t/v t/ v
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V 20 20 TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A IOH = -2 mA IOH = -8 mA IOH = -16 mA IOL = 50 A IOL = 2 mA IOL = 8 mA IOL = 16 mA VI = 5.5 V or GND VO = VCC or GND VI = VCC or GND, IO = 0 VI or VO = 0 to 5.5 V VI = VCC or GND SN54LV240A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 0 to 5.5 V 5.5 V 5.5 V 0 3.3 V 2.3 MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 5 20 5 2.3 TYP MAX SN74LV240A MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 5 20 5 A A A A pF V TYP MAX UNIT
VOH
V
VOL
II IOZ ICC Ioff Ci
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
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SN54LV240A, SN74LV240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS384F - SEPTEMBER 1997 - REVISED JULY 2003
switching characteristics over recommended operating VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis tpd ten tdis tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. FROM (INPUT) A OE OE A OE OE TO (OUTPUT) Y Y Y Y Y Y CL = 50 pF CL = 15 pF LOAD CAPACITANCE MIN
free-air
temperature
SN74LV240A MIN 1 1 1 1 1 1 MAX 14 17 16 17 21 21 2
range,
UNIT
TA = 25C TYP MAX 11.6 6.3 8.5 14.6 9.7 8.2 10.3 14.2 14.1 14.4 17.8 19.2 2
SN54LV240A MIN 1 1 1 1 1 1 MAX 14 17 16 17 21 21
ns
ns
switching characteristics over recommended operating VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis tpd ten tdis tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. FROM (INPUT) A OE OE A OE OE TO (OUTPUT) Y Y Y Y Y Y CL = 50 pF CL = 15 pF LOAD CAPACITANCE
free-air
temperature
SN74LV240A MIN 1 1 1 1 1 1 MAX 9 12.5 13.5 12.5 16 17 1.5
range,
UNIT
TA = 25C MIN TYP MAX 4.6 7.5 10.6 6.2 8.3 5.9 7.5 11.8 12.5 11 14.1 15 1.5
SN54LV240A MIN 1 1 1 1 1 1 MAX 9 12.5 13.5 12.5 16 17
ns
ns
switching characteristics over recommended operating VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis tpd ten tdis tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. FROM (INPUT) A OE OE A OE OE TO (OUTPUT) Y Y Y Y Y Y CL = 50 pF CL = 15 pF LOAD CAPACITANCE MIN
free-air
temperature
SN74LV240A MIN 1 1 1 1 1 1 MAX 6.5 8.5 13.5 8.5 10.5 15.5 1
range,
UNIT
TA = 25C TYP MAX 3.4 5.5 4.6 7.4 4.4 5.6 9.7 7.3 12.2 7.5 9.3 14.2 1
SN54LV240A MIN 1 1 1 1 1 1 MAX 6.5 8.5 13.5 8.5 10.5 15.5
ns
ns
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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5
SN54LV240A, SN74LV240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS384F - SEPTEMBER 1997 - REVISED JULY 2003
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 5)
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 2.31 0.99 SN74LV240A MIN TYP 0.56 -0.49 2.82 MAX UNIT V V V V V
VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz VCC 3.3 V 5V TYP 14 16.4 UNIT pF
6
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SN54LV240A, SN74LV240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS384F - SEPTEMBER 1997 - REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC 0V VCC tsu Data Input 0V 50% VCC th VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC 50% VCC tPZL Output Waveform 1 S1 at VCC (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B) 50% VCC 50% VCC 50% VCC 0V tPLZ VCC VOL + 0.3 V VOL tPHZ VOH - 0.3 V VOH 0 V
tw
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
50% VCC
50% VCC tPHL
0V
Output Control
50% VCC
VOH 50% VCC VOL tPLH
50% VCC
VOH 50% VCC VOL
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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7
MECHANICAL DATA
MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000
DGV (R-PDSO-G**)
24 PINS SHOWN 0,23 0,13 13
PLASTIC SMALL-OUTLINE
0,40 24
0,07 M
0,16 NOM 4,50 4,30 6,60 6,20
Gage Plane
0,25 0- 8 1 A 12 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,08
PINS ** DIM A MAX A MIN
14 3,70 3,50
16 3,70 3,50
20 5,10 4,90
24 5,10 4,90
38 7,90 7,70
48 9,80 9,60
56 11,40 11,20
4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194
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1
MECHANICAL DATA
MSOI003E - JANUARY 1995 - REVISED SEPTEMBER 2001
DW (R-PDSO-G**)
16 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 9
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 16
0.010 (0,25)
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.291 (7,39) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** DIM A MAX 0.004 (0,10)
16 0.410 (10,41) 0.400 (10,16)
18 0.462 (11,73) 0.453 (11,51)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78) 4040000/E 08/01
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
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1
MECHANICAL DATA
MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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1
MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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1
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